The present invention relates generally to digital data processing, and more particularly to an improved digital data separator.
Digital data is conventionally stored on a floppy disk in one of several codes or formats. Self-clocking Manchester codes (FM, MFM, Biphase, MMFM, RLL 2,7 and the like) are widely used in data stored on disks, particularly in magnetic storage and data communications. The data coded in accordance with these and other codes contains both clock and data information in a common data stream. In order to utilize the data from the disk, a data separator is typically provided to separate the data from the clock and to provide separate data and clock signals for use by an external utilization device, such as a disk controller.
Because of the noise and jitter that typically occur in the data stream from the disk, and possible variations in the rotational speed of the floppy disk, the data separator must also be able to maintain synchronization between the reconstructed reference clock and the input data and to make necessary adjustments in the reference clock for variations in the frequency or period of the input data received from the disk so as to maintain the regenerated data pulsed in the middle of a half bit cell or data window. One widely used technique for separating data and developing a reference clock from the encoded data stream involves the use of an analog phase-locked loop. The analog circuits used in an analog phase-locked loop, however, are generally more expensive and less reliable than digital circuitry. For this reason attempts have been made in recent years to implement phase-locked loops for use in data separators that employ digital circuits and techniques. One prior approach to the digital implementation of a phase-locked loop is described in U.S. Pat. No. 4,472,818, which issued to John M. Zapisek and is assigned to the assignee of the present application.
Although the known digital data separators, such as the one described in the aforesaid patent, have proven to be successful in many applications, they generally require high clock rates in order to achieve acceptable performance, particularly with respect to accuracy and resolution. As a consequence of the requirement of a high clock rate, it is generally not cost effective to implement these known digital data separators in MOS integrated circuits. In addition, some of the known digital data separators compromise performance, such as bit jitter tolerance, to allow them to operate at a lower clock rate.
The conventional digital data separators typically correct the data in the data window to a best-case resolution of plus or minus one operating clock period. For this reason, the more accurate digital data separators employ both short-term (phase) and long-term (period) corrections to the data in order to achieve acceptable accuracy. The phase correction compensates for relatively fast data window distortions (such as bit jitter), whereas the period correction compensates for slow distortions (such as motor speed variation). Each of these corrections attempts to place the separated data pulse in the middle of the correct data window. These techniques, however, have several drawbacks relating to the slow clock speeds and the resultant poor resolution.